The stacking of integrated circuits and discrete devices in three dimensions enables advanced Chip Packaging, CMOS, and mixed CMOS/Photonics/RF technologies and applications. An inability to precisely align structures and bond them to each other with minimum yield impact is a major limitation to three-dimensional integrated circuit fabrication. Many process schemes are employed to transfer devices from one Si wafer and stack them on devices fabricated on another Si wafer. Generally either direct bonding of two Si wafers with the subsequent removal of one (donor) substrate, or a (donor) layer transfer to a disposable “handle” substrate with subsequent bonding and handle substrate removal are methods used for circuit and device level 3D integration. These processes have limitations that induce manufacturing complexity and can reduce yields.
Directly bonding two silicon wafers face to face and selectively grinding and etching one to leave a transferred device layer is an option that does not involve processing of thermally dissimilar materials. In the device or circuit alignment procedure, however, this technique does not allow direct viewing of alignment patterns and through wafer imaging using infrared light is often used to see through each Si wafer during the alignment procedure. Transfer of device layers from donor substrates to transparent “handle” substrates allows direct optical alignment of patterns, but introduces pattern shifts and yield limitations as a result of unmatched thermal characteristics and substrate flatness variations.
Three-dimensional integrated circuit fabrication techniques also often suffer from process induced pattern specific voiding at the bonding surface. Such voiding is often very difficult to control and reduces product yields.
Therefore a need exists to overcome the problems with the prior art as discussed above.